60 lines
1.4 KiB
Verilog
60 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2000 Yasuhisa Kato <ykato@mac.com>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module drvz( clk, iA, iC, ioS );
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input clk, iA, iC ;
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inout ioS ;
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assign ioS = (iC) ? iA : 'bz ;
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endmodule
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module main;
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reg clk, c ;
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initial begin clk = 0 ; forever #5 clk = ~clk ; end
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initial begin c = 0 ; #40 $finish(0); end
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wire a, b, s ;
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assign a = 'b0 ;
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assign b = 'b1 ;
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always @(posedge clk) c <= ~c ;
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drvz M ( clk, a, c, s ) ;
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drvz N ( clk, b, ~c, s ) ; // line(A)
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always @(posedge clk)
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$display("%b %b %b", s, a, b );
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endmodule
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// expected output
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// 1 0 1
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// 0 0 1
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// 1 0 1
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// 0 0 1
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// ivl 0.3 result
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// x 0 1
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// 0 0 1
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// x 0 1
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// 0 0 1
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