28 lines
522 B
Verilog
28 lines
522 B
Verilog
module test;
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reg [1:0] result;
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initial begin
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$display("hello world, 'b%b", 1'b1);
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result = get_bytes(4'b0111);
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end
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function [1:0] get_bytes;
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input [3:0] in_byte_enable;
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reg my_byte;
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begin
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my_byte = 3;
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begin: while_block
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while (in_byte_enable[my_byte] == 1)
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begin
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$display("Byte enable is 'h%h", my_byte);
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if(my_byte == 0)
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disable while_block;
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my_byte = my_byte - 1;
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end
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end
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get_bytes = 2'b11;
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end
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endfunction
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endmodule
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