78 lines
1.8 KiB
Verilog
78 lines
1.8 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate defparam
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module main ();
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reg clock;
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reg q;
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reg reset;
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reg error;
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always @(posedge clock or posedge reset)
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begin : FF
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# 2;
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if(reset)
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q <= 0;
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else
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q <= ~q;
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end
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initial
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begin
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// Set reset to init f/f.
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error = 0;
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clock = 0;
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reset = 1;
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#4 ;
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if(q != 1'b0)
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begin
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$display("FAILED - disable3.6A - Flop didn't clear on clock & reset");
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error = 1;
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end
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reset = 1'b0;
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clock = 1'b1;
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# 3;
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if(q != 1'b1)
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begin
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$display("FAILED - disable3.6A - Flop didn't set on clock");
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error = 1;
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end
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clock = 1'b0;
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# 3;
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clock = 1'b1; // Now cause the toggle edge
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# 1;
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disable FF; // And disable the toggle event
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# 2;
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if(q != 1'b1)
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begin
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$display("FAILED - disable3.6A - Disable didn't stop FF toggle");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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