55 lines
827 B
Verilog
55 lines
827 B
Verilog
module top();
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reg CLK;
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reg [3:0] D;
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reg EN1;
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reg EN2;
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reg EN3;
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reg [3:0] Q;
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always @(posedge CLK) begin
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if (EN1) Q[1] <= D[1];
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if (EN2) Q[2] <= D[2];
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if (EN3) Q[3] <= D[3];
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end
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reg failed;
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(* ivl_synthesis_off *)
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initial begin
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failed = 0;
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$monitor("%b %b %b %b %b %b", CLK, EN1, EN2, EN3, D, Q);
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CLK = 0;
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EN1 = 0;
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EN2 = 0;
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EN3 = 0;
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D = 4'b0000;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 4'bxxxx) failed = 1;
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EN1 = 1;
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D = 4'b0000;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 4'bxx0x) failed = 1;
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EN1 = 0;
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EN2 = 1;
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D = 4'b1111;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 4'bx10x) failed = 1;
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EN2 = 0;
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EN3 = 1;
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D = 4'b0000;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 4'b010x) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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