61 lines
934 B
Verilog
61 lines
934 B
Verilog
module dff();
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reg clk;
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reg rst;
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reg ce;
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reg [3:0] d;
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reg [3:0] q;
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always @(negedge clk or posedge rst) begin
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if (rst)
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q <= 4'b1001;
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else if (ce)
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q <= d;
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end
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(* ivl_synthesis_off *)
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reg failed = 0;
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initial begin
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$monitor("%b %b %b %b", rst, clk, d, q);
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clk = 1'b0;
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ce = 1'b0;
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rst = 1'b0;
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d = 4'b0110;
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#1;
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if (q !== 4'bxxxx) failed = 1;
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rst = 1'b1;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b1;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b0;
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#1;
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if (q !== 4'b1001) failed = 1;
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rst = 1'b0;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b1;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b0;
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#1;
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if (q !== 4'b1001) failed = 1;
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ce = 1'b1;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b1;
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#1;
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if (q !== 4'b1001) failed = 1;
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clk = 1'b0;
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#1;
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if (q !== 4'b0110) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule // dff
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