53 lines
840 B
Verilog
53 lines
840 B
Verilog
module main;
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reg clk;
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reg Q, D, ce;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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if (ce)
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begin
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end
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else
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Q <= D;
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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ce = 0;
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D = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1'b0) begin
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$display("FAILED --- initial setup failed: Q=%b, D=%b, ce=%b",
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Q, D, ce);
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$finish;
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end
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ce = 1;
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D = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1'b0) begin
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$display("FAILED --- disable didnot work: Q=%b, D=%b, ce=%b",
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Q, D, ce);
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$finish;
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end
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ce = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1'b1) begin
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$display("FAILED --- disabled disable not OK: Q=%b, D=%b, ce=%b",
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Q, D, ce);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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