73 lines
1.2 KiB
Verilog
73 lines
1.2 KiB
Verilog
module main;
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reg [3:0] count;
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reg CLOCK;
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reg RSTn, SETn;
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(* ivl_synthesis_off *)
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initial begin
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CLOCK = 0;
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RSTn = 0;
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SETn = 1;
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#1 CLOCK = 1;
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#1 CLOCK = 0;
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if (count !== 4'b0000) begin
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$display("FAILED -- initial reset doesn't");
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$finish;
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end
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RSTn = 1;
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#1 CLOCK = 1;
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#1 CLOCK = 0;
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#1 CLOCK = 1;
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#1 CLOCK = 0;
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if (count !== 4'b0010) begin
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$display("FAILED -- count up is %b", count);
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$finish;
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end
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SETn = 0;
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#1 ;
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if (count !== 4'b1101) begin
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$display("FAILED -- Aset failed: count=%b", count);
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$finish;
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end
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SETn = 1;
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#1 CLOCK = 1;
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#1 CLOCK = 0;
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if (count !== 4'b1110) begin
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$display("FAILED -- Aset didn't release: count=%b", count);
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$finish;
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end
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RSTn = 0;
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#1 ;
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if (count !== 4'b0000) begin
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$display("FAILED -- Aclr failed: count=%b", count);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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(* ivl_synthesis_on *)
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always @(posedge CLOCK or negedge RSTn or negedge SETn)
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begin
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if (!RSTn)
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count =0; //async clear
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else
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if (!SETn)
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count = 4'b1101; //async set
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else
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count = count + 1;
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end
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endmodule
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