71 lines
1.8 KiB
Verilog
71 lines
1.8 KiB
Verilog
// Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// This tests DFF-like behavior. The clocked always block acts like a
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// DFF, and if the -Fsynth flag to ivl is used, actually generates an
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// LPM_FF device.
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module main () ;
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reg clk;
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reg D, Q;
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always #10 clk = ~clk;
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always @(posedge clk) Q = D;
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initial begin
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clk = 0;
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D = 0;
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@(negedge clk)
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if (Q !== 1'b0)
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begin
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$display("FAILED: %b !== %b", Q, D);
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$finish;
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end
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D = 1;
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@(negedge clk)
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if (Q !== 1'b1)
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begin
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$display("FAILED: %b !== %b", Q, D);
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$finish;
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end
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D = 'bx;
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@(negedge clk)
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if (Q !== 1'bx)
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begin
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$display("FAILED: %b !== %b", Q, D);
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$finish;
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end
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D = 'bz;
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@(negedge clk)
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if (Q !== 1'bz)
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begin
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$display("FAILED: %b !== %b", Q, D);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule
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