48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
`begin_keywords "1364-2005"
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`timescale 1ns/100ps
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module top;
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parameter pdly = 1.2;
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real rdly = 1.3;
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integer idly = 1;
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reg in = 1'b0;
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wire gi, gf, gs, gt;
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wire #idly int = in;
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wire #1.1 first = in;
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wire #pdly second = in;
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wire #rdly third = in;
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buf #idly (gi, in);
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buf #1.1 (gf, in);
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buf #pdly (gs, in);
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buf #rdly (gt, in);
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initial begin
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$monitor($realtime,, int,, first,, second,, third,, gi,, gf,, gs,, gt);
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#0 in = 1'b1;
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#2 in = 1'b0;
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#4;
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rdly = -6.1; // Since we are at 6 this will not wrap.
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in = 1'b1;
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@(third or gt) $display("Large delay: ", $realtime);
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end
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initial #1.1 $display("Should be 1.1: ", $realtime); // This should be 1.1
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initial #pdly $display("Should be 1.2: ", $realtime); // This should be 1.2
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initial begin
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#0; // We need this so that rdly has a defined value.
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#rdly $display("Should be 1.3: ", $realtime); // This should be 1.3
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end
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initial begin
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#0; // We need this so that rdly has a defined value.
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#idly $display("Should be 1.0: ", $realtime); // This should be 1.0
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end
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endmodule
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`timescale 1ns/1ps
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module top2;
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initial #1.001 $display("Should be 1.001: ", $realtime);
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endmodule
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`end_keywords
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