49 lines
1.3 KiB
Verilog
49 lines
1.3 KiB
Verilog
//
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// Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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/*
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* This function captures the correctness of a non-constant delay
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* that is internal to a non-blocking assignment.
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*/
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module main;
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reg [7:0] delay = 0;
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reg step;
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initial begin
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delay = 2;
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step = 0;
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step <= #(delay) 1;
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#1 if (step !== 0) begin
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$display("FAILED -- step=%b at time=1", step);
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$finish;
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end
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#2 if (step !== 1) begin
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$display("FAILED == step=%b at time=3", step);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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