58 lines
1.3 KiB
Verilog
58 lines
1.3 KiB
Verilog
module main;
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time period;
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reg drive;
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// This is the main point of the test. Non-constant delay expressions
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// should work here.
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wire #(period/3) trace = drive;
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initial begin
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period = 8*3;
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// Initially, set up a period=8 and get the trace to start
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// following the drive.
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#1 drive <= 1;
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#9 if (trace !== drive) begin
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$display("FAILED -- time=%0t, drive=%b, trace=%b",
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$time, drive, trace);
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$finish;
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end
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// The drive should NOT change the trace before the period.
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drive <= 0;
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#7 if (trace !== 1'b1) begin
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$display("FAILED -- time=%0t, drive=%b, trace=%b",
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$time, drive, trace);
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$finish;
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end
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#2 if (trace !== drive) begin
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$display("FAILED -- time=%0t, drive=%b, trace=%b",
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$time, drive, trace);
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$finish;
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end
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// Change the period.
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period = 6*3;
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// Now check that the new delay is taken.
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#1 drive <= 1;
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#5 if (trace !== 1'b0) begin
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$display("FAILED -- time=%0t, drive=%b, trace=%b",
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$time, drive, trace);
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$finish;
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end
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#2 if (trace !== drive) begin
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$display("FAILED -- time=%0t, drive=%b, trace=%b",
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$time, drive, trace);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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