115 lines
2.6 KiB
Verilog
115 lines
2.6 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate defparam
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module module_a (out0,in0);
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input in0;
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output [5:0] out0;
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parameter [5:0] ident0 = 0;
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parameter [5:0] ident1 = 5'h11;
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reg [5:0] out0;
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// Basic MUX switches on in0
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always @ (in0)
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begin
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if(in0)
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out0 = ident0;
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else
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out0 = ident1;
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end
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endmodule // module_a
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module module_b (out0,out1,in0,in1);
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input in0;
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input in1;
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output [5:0] out0;
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output [5:0] out1;
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module_a testmodA (.out0(out0),.in0(in0));
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module_a testmodB (.out0(out1),.in0(in1));
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endmodule // module_b
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module main ();
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reg in0,in1;
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reg error;
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wire [5:0] out0,out1;
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defparam NameB.testmodA.ident0 = 5'h4;
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defparam NameB.testmodB.ident0 = 5'h5;
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defparam NameB.testmodB.ident1 = 5'h6;
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module_b NameB (.out0(out0),.out1(out1),
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.in0(in0),.in1(in1));
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initial
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begin
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error = 0;
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#1 ;
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in0 = 0;
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#1 ;
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if(out0 != 5'h11)
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begin
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$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
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$display("out0 = %h",out0);
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error = 1;
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end
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#1 ;
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in0 = 1;
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#1 ;
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if(out0 != 5'h4)
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begin
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$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
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error = 1;
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end
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#1;
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in1 = 0;
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#1;
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if(out0 != 5'h4) // Validate the 0 side didn't change!
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begin
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$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
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error = 1;
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end
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if(out1 != 5'h6)
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begin
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$display("FAILED - defparam3.5A - Defparam testmodB.ident1");
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error = 1;
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end
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#1;
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in1 = 1;
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#1;
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if(out1 != 5'h5)
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begin
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$display("FAILED - defparam3.5A - Defparam testmodB.ident0");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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