77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate defparam with list
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//
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module NameA ();
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parameter ident0 = 12;
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parameter ident1 = 20 ;
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wire [31:0] value0 = ident0;
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wire [31:0] value1 = ident1;
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endmodule
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module main ();
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defparam main.testmodA.ident0 = 15; // Validate single val
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defparam main.testmodB.ident1 = 16, // Validate list of vals
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main.testmodB.ident0 = 17; // Validate single val
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reg error;
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NameA testmodA ();
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NameA testmodB ();
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initial
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begin
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error = 0;
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# 1;
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if(main.testmodA.value0 !== 15)
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begin
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error = 1;
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$display("FAILED - defparam.v main.testmodA.value0 != 15");
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end
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# 1;
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if(main.testmodA.value1 !== 20)
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begin
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error = 1;
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$display("FAILED - defparam.v main.testmodA.value1 != 20");
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end
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# 1;
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if(main.testmodB.value0 !== 17)
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begin
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error = 1;
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$display("FAILED - defparam.v main.testmodB.value0 != 17");
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end
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# 1;
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if(main.testmodB.value1 !== 16)
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begin
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error = 1;
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$display("FAILED - defparam.v main.testmodB.value1 != 16");
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end
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# 1;
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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