62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This test triggers constant propagation through AND gates.
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*/
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module main;
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wire a = 1'b0;
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wire b = 1'b1;
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wire c = 1'b1;
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wire d = 1'bx;
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wire out0, out1, out2, out3;
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and (out0, a, b); // Should be 0
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and (out1, b, c); // Should be 1
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and (out2, a, d); // Should be 0 because of a
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and (out3, b, d); // Should be x
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initial begin
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#0 if (out0 !== 1'b0) begin
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$display("FAILED -- out0 = %b", out0);
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$finish;
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end
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if (out1 !== 1'b1) begin
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$display("FAILED -- out1 = %b", out1);
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$finish;
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end
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if (out2 !== 1'b0) begin
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$display("FAILED -- out2 = %b", out2);
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$finish;
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end
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if (out3 !== 1'bx) begin
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$display("FAILED -- outx = %b", out3);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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