79 lines
2.0 KiB
Verilog
79 lines
2.0 KiB
Verilog
//
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// Copyright (c) 1999 Steve Wilson (stevew@home.com)
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// Based on code contributed by Peter Monta (pmonta@imedia.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate XOR op using non-blocking assignment
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//
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module main;
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reg [7:0] a;
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reg b;
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reg c;
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reg error;
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initial
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begin
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#1;
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error = 0;
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for(a = 0; a <= 8'h1; a = a + 1)
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begin
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b = 0;
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#1 ;
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if(a)
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begin
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if(!c)
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begin
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$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
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error = 1;
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end
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end
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if(!a)
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begin
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if(c)
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begin
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$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
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error = 1;
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end
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end
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b = 1;
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#1 ;
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if(!a)
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begin
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if(!c)
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begin
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$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
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error = 1;
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end
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end
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if(a)
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begin
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if(c)
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begin
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$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
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error = 1;
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end
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end
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end
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if(!error)
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$display("PASSED");
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end
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always @(a or b)
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c <= a ^ b;
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endmodule
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