74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
// Test binary operators in constant functions
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module constfunc3();
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function [7:0] Add(input [7:0] l, input [7:0] r);
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Add = l + r;
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endfunction
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function [7:0] Mul(input [7:0] l, input [7:0] r);
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Mul = l * r;
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endfunction
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function [7:0] Div(input [7:0] l, input [7:0] r);
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Div = l / r;
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endfunction
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function [7:0] Pow(input [7:0] l, input [7:0] r);
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Pow = l ** r;
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endfunction
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function [7:0] And(input [7:0] l, input [7:0] r);
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And = l & r;
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endfunction
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function [7:0] Shift(input [7:0] l, input [7:0] r);
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Shift = l << r;
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endfunction
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function [7:0] Logic(input [7:0] l, input [7:0] r);
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begin
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Logic[0] = l[0] && r[0];
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Logic[1] = l[1] && r[1];
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Logic[2] = l[2] && r[2];
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Logic[3] = l[3] && r[3];
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Logic[4] = l[4] || r[4];
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Logic[5] = l[5] || r[5];
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Logic[6] = l[6] || r[6];
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Logic[7] = l[7] || r[7];
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end
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endfunction
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localparam [7:0] ResultAdd = Add(8'h0f, 8'h0f);
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localparam [7:0] ResultMul = Mul(8'h0f, 8'h0f);
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localparam [7:0] ResultDiv = Div(8'hf0, 8'h0f);
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localparam [7:0] ResultPow = Pow(8'h02, 8'h05);
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localparam [7:0] ResultAnd = And(8'h0f, 8'h55);
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localparam [7:0] ResultShift = Shift(8'h55, 8'h03);
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localparam [7:0] ResultLogic = Logic(8'h33, 8'h55);
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reg failed;
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initial begin
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failed = 0;
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$display("%h", ResultAdd);
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$display("%h", ResultMul);
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$display("%h", ResultDiv);
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$display("%h", ResultPow);
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$display("%h", ResultAnd);
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$display("%h", ResultShift);
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$display("%h", ResultLogic);
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if (ResultAdd !== 8'h1e) failed = 1;
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if (ResultMul !== 8'he1) failed = 1;
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if (ResultDiv !== 8'h10) failed = 1;
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if (ResultPow !== 8'h20) failed = 1;
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if (ResultAnd !== 8'h05) failed = 1;
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if (ResultShift !== 8'ha8) failed = 1;
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if (ResultLogic !== 8'h71) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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