59 lines
1.0 KiB
Verilog
59 lines
1.0 KiB
Verilog
// Test concatenation inside a constant function
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module constfunc14();
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function [7:0] concat1(input [7:0] value);
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reg [3:0] tmp1;
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reg [3:0] tmp2;
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begin
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{tmp1, tmp2} = {value[3:0], value[7:4]};
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{concat1[3:0], concat1[7:4]} = {tmp2, tmp1};
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end
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endfunction
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function [7:0] concat2(input [7:0] value);
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reg [2:0] tmp1;
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reg [3:0] tmp2;
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begin
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{tmp1, tmp2} = {value[3:0], value[7:4]};
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{concat2[3:0], concat2[7:4]} = {tmp2, tmp1};
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end
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endfunction
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function [7:0] concat3(input [7:0] value);
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reg signed [2:0] tmp1;
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reg signed [2:0] tmp2;
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begin
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{tmp1, tmp2} = {value[2:0], value[6:4]};
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concat3[7:4] = tmp1;
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concat3[3:0] = tmp2;
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end
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endfunction
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localparam res1 = concat1(8'h5a);
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localparam res2 = concat2(8'h5a);
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localparam res3 = concat3(8'h5a);
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reg failed = 0;
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initial begin
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$display("%h", res1); if (res1 !== 8'ha5) failed = 1;
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$display("%h", res2); if (res2 !== 8'ha2) failed = 1;
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$display("%h", res3); if (res3 !== 8'h2d) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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