35 lines
647 B
Verilog
35 lines
647 B
Verilog
// Test repeat statements inside a constant function
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module constfunc11();
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function [31:0] pow2(input [5:0] x);
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begin:body
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pow2 = 1;
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repeat (x) begin
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pow2 = 2 * pow2;
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end
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end
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endfunction
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localparam val0 = pow2(0);
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localparam val1 = pow2(1);
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localparam val2 = pow2(2);
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localparam val3 = pow2(3);
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reg failed;
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initial begin
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failed = 0;
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$display("%0d", val0); if (val0 !== 1) failed = 1;
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$display("%0d", val1); if (val1 !== 2) failed = 1;
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$display("%0d", val2); if (val2 !== 4) failed = 1;
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$display("%0d", val3); if (val3 !== 8) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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