90 lines
2.0 KiB
Verilog
90 lines
2.0 KiB
Verilog
module test();
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wire a;
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tri0 b;
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tri1 c;
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tri1 d;
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tri0 e;
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wire f;
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wire g;
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wire h;
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wire i;
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tri1 j;
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tri0 k;
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wire l;
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tri0 m;
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tri1 n;
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assign d = 1'b0;
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assign e = 1'b1;
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assign f = 1'b0;
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assign f = 1'b1;
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assign g = 1'b1;
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assign g = 1'b0;
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assign (strong1,strong0) h = 1'b0;
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assign ( weak1, weak0) h = 1'b1;
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assign ( weak1, weak0) i = 1'b0;
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assign (strong1,strong0) i = 1'b1;
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assign (pull1,pull0) j = 1'b0;
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assign (pull1,pull0) k = 1'b1;
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wire [1:0] A = {1'b1, a};
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wire [1:0] B = {1'b1, b};
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wire [1:0] C = {1'b1, c};
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wire [1:0] D = {1'b1, d};
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wire [1:0] E = {1'b1, e};
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wire [1:0] F = {1'b1, f};
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wire [1:0] G = {1'b1, g};
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wire [1:0] H = {1'b1, h};
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wire [1:0] I = {1'b1, i};
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wire [1:0] J = {1'b1, j};
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wire [1:0] K = {1'b1, k};
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wire [1:0] L = {1'b1, l};
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wire [1:0] M = {1'b1, m};
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wire [1:0] N = {1'b1, n};
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reg failed;
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initial begin
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failed = 0; #1;
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$display("A = %b, expect 1z", A); if (A !== 2'b1z) failed = 1;
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$display("B = %b, expect 10", B); if (B !== 2'b10) failed = 1;
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$display("C = %b, expect 11", C); if (C !== 2'b11) failed = 1;
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$display("D = %b, expect 10", D); if (D !== 2'b10) failed = 1;
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$display("E = %b, expect 11", E); if (E !== 2'b11) failed = 1;
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$display("F = %b, expect 1x", F); if (F !== 2'b1x) failed = 1;
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$display("G = %b, expect 1x", G); if (G !== 2'b1x) failed = 1;
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$display("H = %b, expect 10", H); if (H !== 2'b10) failed = 1;
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$display("I = %b, expect 11", I); if (I !== 2'b11) failed = 1;
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$display("J = %b, expect 1x", J); if (J !== 2'b1x) failed = 1;
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$display("K = %b, expect 1x", K); if (K !== 2'b1x) failed = 1;
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force l = 1'b0; #1;
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$display("L = %b, expect 10", L); if (L !== 2'b10) failed = 1;
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force l = 1'b1; #1;
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$display("L = %b, expect 11", L); if (L !== 2'b11) failed = 1;
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force m = 1'b1; #1;
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$display("M = %b, expect 11", M); if (M !== 2'b11) failed = 1;
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force n = 1'b0; #1;
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$display("N = %b, expect 10", N); if (N !== 2'b10) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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