64 lines
1.6 KiB
Verilog
64 lines
1.6 KiB
Verilog
//
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// Copyright (c) 1999 Paul Bain (pdbain@adm.org)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - PR122 - Const define without length specification causes error.
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`timescale 1ns/1ns
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module main(
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clk,
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dat
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);
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parameter dat_width =32;
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input clk;
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output [dat_width-1:0] dat;
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reg [dat_width-1:0] dat;
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reg [32-1:0] exp_dat;
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reg error;
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initial
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begin
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exp_dat = 0;
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dat = 0;
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end
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initial
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begin
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dat = #1 'h00010203;
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exp_dat = #1 'h0010203;
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error = 0;
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#10;
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for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1)
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begin
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dat = exp_dat;
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#1
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if(dat !== exp_dat)
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begin
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$display("ERROR: dat = %h, exp_dat = %h",dat,exp_dat);
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error = 1;
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end
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else
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$display("Okay: dat = %h, exp_dat = %h",dat,exp_dat);
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end
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if(error === 0)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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