99 lines
1.5 KiB
Verilog
99 lines
1.5 KiB
Verilog
module main;
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reg [2:0] Q;
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reg clk, clr, up, down;
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reg flag;
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(*ivl_synthesis_off *)
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initial begin
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clk = 0;
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up = 0;
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down = 0;
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clr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED");
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$finish;
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end
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if (flag !== 0) begin
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$display("FAILED");
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$finish;
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end
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up = 1;
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clr = 0;
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 3'b010) begin
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$display("FAILED");
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$finish;
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end
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if (flag !== 0) begin
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$display("FAILED");
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$finish;
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end
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up = 0;
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down = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 3'b001) begin
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$display("FAILED");
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$finish;
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end
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if (flag !== 0) begin
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$display("FAILED");
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$finish;
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end
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down = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 3'b001) begin
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$display("FAILED");
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$finish;
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end
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if (flag !== 1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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/*
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* This statement models a snythesizable UP/DOWN counter. The up
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* and down cases are enabled by up and down signals. If both
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* signals are absent, the synthesizer should take the implicit
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* case that Q <= Q;
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*/
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(* ivl_synthesis_on *)
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always @(posedge clk, posedge clr)
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if (clr) begin
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Q <= 0;
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flag <= 0;
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end else begin
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if (up)
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Q <= Q + 1;
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else if (down)
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Q <= Q - 1;
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else
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flag <= 1;
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end
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endmodule // main
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