24 lines
570 B
Verilog
24 lines
570 B
Verilog
module top;
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// These should create two ufunc calls each and the zero replication one
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// will not be connected to anything.
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wire [31:0] var1 = {{0{ufunc(0)}}, ufunc(0)};
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wire [31:0] var2 = {ufunc(0), {0{ufunc(0)}}};
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integer fres;
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initial begin
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#1;
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if (fres != 4) $display("FAILED, expected fres = 4, got %0d", fres);
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else $display("PASSED");
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end
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function integer ufunc;
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input in;
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begin
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if (fres === 32'bx) fres = 0;
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if (in) fres = fres - 1;
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else fres = fres + 1;
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ufunc = fres;
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end
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endfunction
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endmodule
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