55 lines
1.5 KiB
Verilog
55 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This tests that parameters can be used in concatenations if
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* the expression it represents has definite width. This test
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* is based on PR#282.
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*/
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module t;
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parameter
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SET = 1'b1,
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CLR = 1'b0,
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S1 = 2'd1,
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HINC = 3'd4;
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//bit signif 12:11, 10 , 9 , 8 , 7, 6 , 5 , 4 , 3 ,2:0
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parameter
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x = {S1,CLR,CLR,CLR,CLR,SET,SET,CLR,CLR,HINC };
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initial begin
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$display("x=%b, $sizeof(x)=%d", x, $sizeof(x));
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if (x !== 13'b0100001100100) begin
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$display("FAILED -- x is %b", x);
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$finish;
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end
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if ($sizeof(x) != 13) begin
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$display("FAILED -- x is %d'b%b", $sizeof(x), x);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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