27 lines
495 B
Verilog
27 lines
495 B
Verilog
module top;
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reg passed;
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reg [7:0] res;
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reg zero;
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reg one;
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initial begin
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passed = 1'b1;
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zero = 1'b0;
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one = 1'b1;
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// res = 1'b1 ? !1'b0/1'b0 : 1'b0;
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res = !1'b0/1'b0;
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if (res !== 8'bx) begin
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$display("FAILED: compiler.");
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passed = 1'b0;
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end
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// res = one ? !1'b0/zero : zero;
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res = !1'b0/zero;
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if (res !== 8'bx) begin
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$display("FAILED: run-time.");
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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