22 lines
641 B
Verilog
22 lines
641 B
Verilog
/*
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* This is a reduced example from comp1001 to demonstrate a problem
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* in the Icarus Verilog code generator. If one addition argument is
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* replaced with a 1-bit register (instead of the constant 1'b1),
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* evaluation is postponed to vvp, which works correctly. It appears
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* that the width of the adder is calculated incorrectly when part
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* of a comparison, but only in constant-propagation mode.
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*/
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module top;
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reg [30:0] r2;
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reg r1=1;
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initial begin
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r2 = (1'b1+1'b1) != 1'bx;
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// r2 = (1'b1+r1) != 1'bx;
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$displayb("r2 = ",r2);
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if (r2 !== 31'b0x) $display("FAILED");
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else $display("PASSED");
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end
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endmodule
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