69 lines
1021 B
Verilog
69 lines
1021 B
Verilog
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module main;
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reg [7:0] val;
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initial begin
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val = 120;
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if (8'd5 < val) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (8'd5 <= val) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (8'd121 > val) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (8'd121 >= val) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (val > 8'd5) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (val >= 8'd5) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (val < 8'd121) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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if (val <= 8'd121) begin
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$display("OK");
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end else begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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