41 lines
985 B
Verilog
41 lines
985 B
Verilog
module top;
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reg nctl, pctl, b;
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wire a, c;
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initial begin
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$monitor(a,c,,"%v",a,,"%v",c,,b,,nctl,,pctl);
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b = 0;
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nctl = 0;
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pctl = 1;
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#1 nctl = 1; pctl = 0;
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#1 nctl = 1; pctl = 1;
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#1 nctl = 0; pctl = 0;
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#1 nctl = 1'bx; pctl = 0;
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#1 nctl = 1; pctl = 1'bx;
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#1 nctl = 1'bx; pctl = 1;
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#1 nctl = 0; pctl = 1'bx;
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#1 nctl = 1'bx; pctl = 1'bx;
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#1 b = 1; nctl = 0; pctl = 1;
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#1 nctl = 1; pctl = 0;
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#1 nctl = 1; pctl = 1;
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#1 nctl = 0; pctl = 0;
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#1 nctl = 1'bx; pctl = 0;
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#1 nctl = 1; pctl = 1'bx;
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#1 nctl = 1'bx; pctl = 1;
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#1 nctl = 0; pctl = 1'bx;
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#1 nctl = 1'bx; pctl = 1'bx;
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#1 b = 1'bx; nctl = 0; pctl = 1;
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#1 b = 1'bx; nctl = 1; pctl = 0;
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#1 b = 1'bx; nctl = 1'bx; pctl = 1'bx;
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#1 b = 1'bz; nctl = 0; pctl = 1;
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#1 b = 1'bz; nctl = 1; pctl = 0;
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#1 b = 1'bz; nctl = 1'bx; pctl = 1'bx;
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end
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nmos n1 (a, b, nctl);
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pmos p1 (a, b, pctl);
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cmos c1 (c, b, nctl, pctl);
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endmodule
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