47 lines
684 B
Verilog
47 lines
684 B
Verilog
/*
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* Author: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
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*
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* The test checks that an unspecified output type is elaborated as Net.
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* If an intial value is given to an unspecified ouput type it does
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* not compile.
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*/
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module clkgen(output clk);
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logic iclk = 'x;
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assign clk = iclk;
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initial begin
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#100;
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disable checking;
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disable gen;
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$display ("PASSED");
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$finish;
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end
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initial begin
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fork
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checking;
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gen;
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join
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end
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task gen;
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begin
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iclk = 0;
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forever #10 iclk = ~iclk;
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end
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endtask
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task checking;
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forever begin
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#1;
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if (clk === 1'bx ) begin
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$display ("FAILED!");
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$finish;
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end
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end
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endtask
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endmodule
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