40 lines
562 B
Verilog
40 lines
562 B
Verilog
/*
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* Author: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
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*
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* The test checks the module bit ouput type accepts default
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* initialization value.
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*/
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module clkgen(output bit clk = 0);
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initial begin
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#100;
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disable checking;
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disable gen;
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$display ("PASSED");
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$finish;
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end
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initial begin
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fork
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gen;
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checking;
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join
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end
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task gen;
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forever #10 clk = ~clk;
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endtask
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task checking;
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forever begin
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#1;
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if (clk ==! 1'b0 && clk ==! 1'b1 ) begin
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$display ("FAILED!");
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$finish;
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end
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end
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endtask
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endmodule
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