77 lines
1.7 KiB
Verilog
77 lines
1.7 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test casting integers to real
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module cast_real();
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int i;
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logic [3:0] l;
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logic signed [3:0] sl;
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real a, b, c, d, e;
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initial begin
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// Initalization using an integer variable
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i = 5;
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a = real'(i);
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// ..and logic
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l = 4'b1010;
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b = real'(l);
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sl = 4'b1010;
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c = real'(sl);
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// Initialization using an integer constant
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d = real'(11);
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e = real'(-7);
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if (a != 5.0)
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begin
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$display("FAILED #1 a = %f", a);
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$finish();
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end
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if (b != 10.0)
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begin
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$display("FAILED #2 b = %f", b);
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$finish();
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end
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if (c != -6.0)
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begin
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$display("FAILED #3 c = %f", c);
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$finish();
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end
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if (d != 11.0)
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begin
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$display("FAILED #4 d = %f", d);
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$finish();
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end
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if (e != -7.0)
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begin
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$display("FAILED #5 e = %f", e);
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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