64 lines
1.1 KiB
Verilog
64 lines
1.1 KiB
Verilog
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module test
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(output reg a,
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output reg b,
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input wire [1:0] sel,
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input wire d
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/* */);
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always @* begin
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b = d;
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case (sel)
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0:
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begin
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a = 0;
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b = 1;
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end
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1:
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begin
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a = 1;
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b = 0;
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end
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default:
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begin
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a = d;
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end
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endcase // case (sel)
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end // always @ *
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endmodule // test
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module main;
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reg [1:0] sel;
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reg d;
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wire a, b;
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test dut (.a(a), .b(b), .sel(sel), .d(d));
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initial begin
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d = 0;
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sel = 0;
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#1 if (a!==0 || b!==1) begin
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$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
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$finish;
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end
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sel = 1;
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#1 if (a!==1 || b!==0) begin
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$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
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$finish;
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end
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sel = 2;
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#1 if (a!==0 || b!==0) begin
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$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
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$finish;
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end
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d = 1;
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#1 if (a!==1 || b!==1) begin
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$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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