24 lines
473 B
Verilog
24 lines
473 B
Verilog
`timescale 10ns/1ps
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module main;
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logic [1:0] counter = 2'b00;
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logic clk = 1'b0;
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initial forever #1 clk <= ~clk;
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always @(posedge clk) begin
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counter <= counter + 2'd1;
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priority case (counter)
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2'd0: $display("case 0");
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2'd1: $display("case 1");
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2'd3: $display("case 3");
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endcase // priority case (counter)
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if (counter == 2'd3) begin
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$display("PASSED");
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$finish(0);
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end
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end
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endmodule
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