32 lines
629 B
Verilog
32 lines
629 B
Verilog
module top;
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reg pass = 1'b1;
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reg [2:0] in;
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real rin;
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wire out, rout;
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assign out = ('d4 == in**2'd2);
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assign rout = (4.0 == rin**2);
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initial begin
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in = 'd0; rin = 0.0;
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#1 if (out != 1'b0 && rout != 1'b0) begin
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$display("FAILED 0/0.0 check");
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pass = 1'b0;
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end
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#1 in = 'd1; rin = 1.0;
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#1 if (out != 1'b0 && rout != 1'b0) begin
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$display("FAILED 1/1.0 check");
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pass = 1'b0;
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end
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#1 in = 'd2; rin = 2.0;
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#1 if (out != 1'b1 && rout != 1'b1) begin
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$display("FAILED 2/2.0 check");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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