77 lines
1001 B
Verilog
77 lines
1001 B
Verilog
module bug();
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function signed [31:0] fpreal(
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input real in
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);
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real m;
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real r;
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begin
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m = 1 << 16;
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r = in * m;
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fpreal = $rtoi(r);
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end
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endfunction
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function signed [31:0] fpdiv(
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input signed [31:0] a,
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input signed [31:0] b
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);
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reg signed [47:0] r;
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begin
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r = a << 16;
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fpdiv = r / b;
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end
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endfunction
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function signed [31:0] fpmul(
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input signed [31:0] a,
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input signed [31:0] b
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);
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reg signed [47:0] r;
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begin
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r = a * b;
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fpmul = r >>> 16;
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end
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endfunction
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function signed [31:0] fppow(
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input signed [31:0] a,
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input real b
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);
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real ar;
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real r;
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begin
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ar = $itor(a) / (1 << 16);
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r = ar ** b;
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fppow = fpreal(r);
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end
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endfunction
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wire signed [31:0] a = 1 << 16;
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wire signed [31:0] b = 4 << 16;
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wire signed [31:0] c = fpdiv(a, b);
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wire signed [31:0] d = fppow(c, 2.0);
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initial begin
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#1 $display("(%0f / %0f)**2.0 = %0f", a / 65536.0, b / 65536.0, d / 65536.0);
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if (d === 32'h0000_1000)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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