40 lines
437 B
Verilog
40 lines
437 B
Verilog
`timescale 1ns/1ps
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module BUFGCE(
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output O,
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input I,
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input CE
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);
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bufif1(O, I, CE);
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specify
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(I => O) = (0.1, 0.2);
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(CE => O) = (0.3, 0.4);
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endspecify
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endmodule
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module dut(
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output out,
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input in,
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input en
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);
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BUFGCE clk_IBUF_BUFG_inst(.O(out), .I(in), .CE(en));
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endmodule
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module top;
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wire out;
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reg in, en;
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dut dut(out, in, en);
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initial begin
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$sdf_annotate("ivltests/br_ml20190814.sdf", dut);
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end
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endmodule
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