42 lines
507 B
Verilog
42 lines
507 B
Verilog
primitive latch(q, e, d);
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output q;
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input e;
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input d;
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reg q;
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table
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// e d | q | q+ |
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1 1 : ? : 1 ;
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1 0 : ? : 0 ;
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0 ? : ? : - ;
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endtable
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endprimitive
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module test();
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wire q;
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reg e;
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reg d;
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reg r;
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latch latch(q, e, d);
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always @(q) begin
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r = 1;
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end
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initial begin
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#1;
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$display("%b %b", q, r);
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// the 'x' should propagate to q before the start of simulation
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if (r === 1'bx && q === 1'bx)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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