luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/ivtest/ivltests/br_ml20181012d.v

6 lines
43 B
Verilog
Raw Blame History

module test();
reg illegal[0];
endmodule
Reference in New Issue View Git Blame Copy Permalink