21 lines
361 B
Verilog
21 lines
361 B
Verilog
module test();
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string str1 = "abcd";
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string str2 = "efgh";
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typedef logic [31:0] vector;
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vector data[1:0];
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initial begin
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data[0] = vector'(str1);
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data[1] = vector'(str2);
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$display("%s %s", data[0], data[1]);
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if (data[0] === "abcd" && data[1] === "efgh")
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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