27 lines
366 B
Verilog
27 lines
366 B
Verilog
module test();
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wire [7:0] value1;
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reg [7:0] value2;
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reg clk;
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assign value1[3:0] = 4'b1010;
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always @(posedge clk) begin
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value2 <= value1;
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end
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(* ivl_synthesis_off *)
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initial begin
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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$display("%b %b", value1, value2);
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if (value2 === 8'bzzzz1010)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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