20 lines
305 B
Verilog
20 lines
305 B
Verilog
module test();
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wire [7:0] value1;
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wire [7:0] value2;
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assign value1[3:0] = 4'd2;
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assign value2 = $itor(value1);
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initial begin
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// 'z' bits are converted to '0'.
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#2 $display("%b %b", value1, value2);
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if (value2 === 8'b00000010)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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