39 lines
593 B
Verilog
39 lines
593 B
Verilog
// Regression test for GitHub issue 9 : Efficiency of verinum and vpp_net
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// pow() functions.
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module bug();
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reg [5:0] ra;
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reg [5:0] ry;
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wire [5:0] wa = 3;
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wire [5:0] wy = wa ** 123456789;
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localparam [5:0] pa = 3;
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localparam [5:0] py = pa ** 123456789;
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reg failed = 0;
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initial begin
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#0;
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ra = 3;
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ry = ra ** 123456789;
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$display("%b", ry);
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if (ry !== 6'b110011) failed = 1;
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$display("%b", wy);
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if (wy !== 6'b110011) failed = 1;
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$display("%b", py);
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if (py !== 6'b110011) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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