35 lines
744 B
Verilog
35 lines
744 B
Verilog
// Regression test for GitHub issue 8 : Signedness handling in binary
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// bitwise operations of constants.
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module bug();
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localparam value1 = 4'sb1010 | 4'sb0000;
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localparam value2 = 4'sb1010 + 4'sb0000;
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localparam value3 = ~4'sb0101;
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localparam value4 = -4'sb0101;
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reg signed [4:0] result;
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reg failed = 0;
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initial begin
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result = value1;
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$display("%b", result);
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if (result !== 5'b11010) failed = 1;
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result = value2;
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$display("%b", result);
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if (result !== 5'b11010) failed = 1;
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result = value3;
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$display("%b", result);
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if (result !== 5'b11010) failed = 1;
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result = value4;
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$display("%b", result);
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if (result !== 5'b11011) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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