22 lines
320 B
Verilog
22 lines
320 B
Verilog
// Regression test for GitHub issue 7 : Undef propagation in power operator.
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module bug();
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reg [3:0] a;
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reg [3:0] y;
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reg failed = 0;
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initial begin
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a = 4'd1 / 4'd0;
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y = 4'd2 ** a;
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$display("%b", a);
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$display("%b", y);
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if (y !== 4'bxxxx)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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