28 lines
566 B
Verilog
28 lines
566 B
Verilog
module test();
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function integer array_value(input integer idx);
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reg [31:0] local_array[1:-1];
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integer i;
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begin
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for (i = -2; i <= 2; i = i + 1) local_array[i] = i;
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array_value = local_array[idx];
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end
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endfunction
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localparam avm2 = array_value(-2);
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localparam avm1 = array_value(-1);
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localparam av0 = array_value(0);
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localparam avp1 = array_value(1);
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localparam avp2 = array_value(2);
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initial begin
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if (avm2 === 'bx && avm1 === -1 && av0 === 0 && avp1 === 1 && avp2 === 'bx)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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