31 lines
519 B
Verilog
31 lines
519 B
Verilog
module tb();
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reg [7:0] in[1:0];
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wire [7:0] out[1:0];
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assign out[0] = $clog2(in[0]);
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assign out[1] = $clog2(in[1]);
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reg failed;
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initial begin
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failed = 0;
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#1 in[0] = 1;
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#1 $display("%0d -> %0d", in[0],out[0]);
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if (out[0] !== 0) failed = 1;
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#1 in[1] = 2;
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#1 $display("%0d -> %0d", in[1],out[1]);
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if (out[1] !== 1) failed = 1;
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#1 in[0] = 3;
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#1 $display("%0d -> %0d", in[0],out[0]);
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if (out[0] !== 2) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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