27 lines
337 B
Verilog
27 lines
337 B
Verilog
module test;
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wire [7:0] val[3:0];
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genvar i;
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for (i = 3; i >= 0; i = i - 1) begin
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assign val[i] = i;
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end
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integer j;
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reg failed = 0;
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initial begin
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for (j = 3; j >= 0; j = j - 1) begin
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$display(val[j]);
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if (val[j] != j) failed = 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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