65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
module top(
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pi_wi, // port implicit, wire implicit
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pi_ws, // port implicit, wire signed
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pi_wu, // port implicit, wire unsigned
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ps_wi, // port signed, wire implicit
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ps_ws, // port signed, wire signed
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ps_wu, // port signed, wire unsigned
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pu_wi, // port unsigned, wire implicit
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pu_ws, // port unsigned, wire signed
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pu_wu // port unsigned, wire unsigned
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);
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output pi_wi;
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output pi_ws;
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output pi_wu;
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output signed ps_wi;
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output signed ps_ws;
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output signed ps_wu;
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output unsigned pu_wi;
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output unsigned pu_ws;
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output unsigned pu_wu;
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wire pi_wi = 1'b1;
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wire ps_wi = 1'b1;
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wire pu_wi = 1'b1;
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wire signed pi_ws = 1'b1;
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wire signed ps_ws = 1'b1;
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wire signed pu_ws = 1'b1;
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wire unsigned pi_wu = 1'b1;
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wire unsigned ps_wu = 1'b1;
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wire unsigned pu_wu = 1'b1;
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reg [1:0] value;
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reg failed = 0;
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initial begin
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#1;
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value = pi_wi; $display("%b", value); if (value !== 2'b01) failed = 1;
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value = pi_ws; $display("%b", value); if (value !== 2'b11) failed = 1;
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value = pi_wu; $display("%b", value); if (value !== 2'b01) failed = 1;
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value = ps_wi; $display("%b", value); if (value !== 2'b11) failed = 1;
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value = ps_ws; $display("%b", value); if (value !== 2'b11) failed = 1;
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value = ps_wu; $display("%b", value); if (value !== 2'b11) failed = 1;
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value = pu_wi; $display("%b", value); if (value !== 2'b01) failed = 1;
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value = pu_ws; $display("%b", value); if (value !== 2'b11) failed = 1;
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value = pu_wu; $display("%b", value); if (value !== 2'b01) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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