30 lines
428 B
Verilog
30 lines
428 B
Verilog
typedef struct packed {
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union packed {
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logic[2:0] a;
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logic[2:0] b;
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} u;
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} s1;
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module top();
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s1 source;
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logic result;
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logic failed = 0;
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initial begin
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source.u.a = 3'b000;
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result = | source.u.b;
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if (result !== 1'b0) failed = 1;
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source.u.a = 3'b001;
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result = | source.u.b;
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if (result !== 1'b1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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