28 lines
395 B
Verilog
28 lines
395 B
Verilog
module test;
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reg [7:0] array[7:0];
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reg [2:0] index;
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reg [7:0] value;
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reg failed = 0;
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initial begin
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array[0] = 1;
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index = 7;
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value = array[index + 1];
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$display("%h", value);
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if (value !== 8'bx) failed = 1;
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value = array[index + 3'd1];
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$display("%h", value);
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if (value !== 8'd1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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