43 lines
1.8 KiB
Verilog
43 lines
1.8 KiB
Verilog
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
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// compile-time errors. If they are not, this test should pass.
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module top;
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reg [3:0][3:0] array;
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reg failed = 0;
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initial begin
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array = 16'h4321;
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$display("%h", array[-2+:2]); if (array[-2+:2] !== 8'hxx) failed = 1;
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$display("%h", array[-1+:2]); if (array[-1+:2] !== 8'h1x) failed = 1;
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$display("%h", array[ 0+:2]); if (array[ 0+:2] !== 8'h21) failed = 1;
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$display("%h", array[ 1+:2]); if (array[ 1+:2] !== 8'h32) failed = 1;
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$display("%h", array[ 2+:2]); if (array[ 2+:2] !== 8'h43) failed = 1;
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$display("%h", array[ 3+:2]); if (array[ 3+:2] !== 8'hx4) failed = 1;
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$display("%h", array[ 4+:2]); if (array[ 4+:2] !== 8'hxx) failed = 1;
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$display("%h", array[-1-:2]); if (array[-1-:2] !== 8'hxx) failed = 1;
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$display("%h", array[ 0-:2]); if (array[ 0-:2] !== 8'h1x) failed = 1;
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$display("%h", array[ 1-:2]); if (array[ 1-:2] !== 8'h21) failed = 1;
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$display("%h", array[ 2-:2]); if (array[ 2-:2] !== 8'h32) failed = 1;
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$display("%h", array[ 3-:2]); if (array[ 3-:2] !== 8'h43) failed = 1;
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$display("%h", array[ 4-:2]); if (array[ 4-:2] !== 8'hx4) failed = 1;
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$display("%h", array[ 5-:2]); if (array[ 5-:2] !== 8'hxx) failed = 1;
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$display("%h", array[-1:-2]); if (array[-1:-2] !== 8'hxx) failed = 1;
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$display("%h", array[ 0:-1]); if (array[ 0:-1] !== 8'h1x) failed = 1;
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$display("%h", array[ 1:0 ]); if (array[ 1:0 ] !== 8'h21) failed = 1;
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$display("%h", array[ 2:1 ]); if (array[ 2:1 ] !== 8'h32) failed = 1;
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$display("%h", array[ 3:2 ]); if (array[ 3:2 ] !== 8'h43) failed = 1;
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$display("%h", array[ 4:3 ]); if (array[ 4:3 ] !== 8'hx4) failed = 1;
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$display("%h", array[ 5:4 ]); if (array[ 5:4 ] !== 8'hxx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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